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<p>Structure type to access the Memory Protection Unit (MPU).  
</p>
<table class="memberdecls">
<tr><td colspan="2"><h2><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a6ae8a8c3a4909ae41447168d793608f7">TYPE</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/ ) MPU Type Register.  <a href="#a6ae8a8c3a4909ae41447168d793608f7"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#aab33593671948b93b1c0908d78779328">CTRL</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x004 (R/W) MPU Control Register.  <a href="#aab33593671948b93b1c0908d78779328"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#afd8de96a5d574c3953e2106e782f9833">RNR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x008 (R/W) MPU Region RNRber Register.  <a href="#afd8de96a5d574c3953e2106e782f9833"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a3f2e2448a77aadacd9f394f6c4c708d9">RBAR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x00C (R/W) MPU Region Base Address Register.  <a href="#a3f2e2448a77aadacd9f394f6c4c708d9"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#adc65d266d15ce9ba57b3d127e8267f03">RASR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x010 (R/W) MPU Region Attribute and Size Register.  <a href="#adc65d266d15ce9ba57b3d127e8267f03"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a4dbcffa0a71c31e521b645b34b40e639">RBAR_A1</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register.  <a href="#a4dbcffa0a71c31e521b645b34b40e639"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a94222f9a8637b5329016e18f08af7185">RASR_A1</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register.  <a href="#a94222f9a8637b5329016e18f08af7185"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a8703a00626dba046b841c0db6c78c395">RBAR_A2</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register.  <a href="#a8703a00626dba046b841c0db6c78c395"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a0aac7727a6225c6aa00627c36d51d014">RASR_A2</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register.  <a href="#a0aac7727a6225c6aa00627c36d51d014"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a9fda17c37b85ef317c7c8688ff8c5804">RBAR_A3</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register.  <a href="#a9fda17c37b85ef317c7c8688ff8c5804"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#aced0b908173b9a4bae4f59452f0cdb0d">RASR_A3</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register.  <a href="#aced0b908173b9a4bae4f59452f0cdb0d"></a><br/></td></tr>
</table>
<hr/><h2>Field Documentation</h2>
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